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A High Efficiency Power Amplifier Integrated with a CPW Patch Antenna
A First Design Iteration
Angielski
145 b
Nawet do 30 dni na zwrot
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112.40
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55.58
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In this work, the CPW-fed aperture-coupled patch antenna is studied for the purpose of integration with a high efficiency power amplifier. The design of a high-efficiency power amplifier using an active multi-harmonic load-pull system is described. The load-pull system is constructed using six-port circuits and can independently vary the output load of a transistor at its fundamental operating frequency, as well as at the second and third harmonics. The system is used to find the efficiency-optimizing output loads of a commercial transistor operating at a class B bias point. A power amplifier with a gain of 7.1 dB and a PAE of 58.6% operating at a fundamental frequency of 3.5 GHz with an input power of 4mW is obtained. A CPW-fed slot-coupled patch antenna is designed to act as both a radiating element and an impedance element, producing the transistor s experimentally determined efficiency-optimizing load at the fundamental frequency. A CPW circuit comprising of internally patterned series stubs is added to the input of the antenna in order to produce the transistor's optimal loads at the second- and third-harmonic frequencies.
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