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Flip-Flop Design in Nanometer CMOS
From High Speed to Low Energy
Angielski
249 b
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This book provides a unified treatment of Flip-Flop/latch design and selection in nanometer CMOS VLSI systems. The design aspects related to the energy-delay tradeoff in Flip-Flops and latches are discussed, given their optimal selection according to the application, and the detailed circuit design in nanometer CMOS VLSI systems. Design strategies are derived in a coherent framework that includes explicitly nanometer effects, including leakage, layout parasitics and process/voltage/temperature variations. The related design tradeoffs are explored in a wide range of applications and energy-performance targets. A wide range of existing and recently proposed Flip-flop and latch topologies are discussed. Theoretical foundations are provided to set the stage for the comprehension of the design guidelines, and emphasis is given on practical aspects and consequences of the presented results. Analytical models and derivations are introduced when needed to gain an insight into the inter-dependence of design parameters under practical constraints.
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