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High-Speed CMOS Transceiver
Principles, Design and Implementation using Multi-level (4-PAM) Signaling
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507 b
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With the exponential growth in speed and integration levels of integrated circuits (ICs), the inter-connection bandwidth between chips is becoming the major performance-limiting factor with modern digital systems. High-speed links in the Gbps ranges have been traditionally implemented in GaAs or bipolar technologies. However, CMOS, despite its slower device speed, is now becoming the target technology of choice for high-speed integrated systems due to its widespread availability and higher integration levels possible. This book explores various signaling techniques and circuit architectures for designing a low-cost high-speed serial link in CMOS technology with the objective of maximizing the operating bandwidth and transmission distance. The book provides a thorough overview of the principles, challenges and concepts involved in high-speed transceiver design and describes how to implement a transceiver in CMOS with detailed circuit schematics and simulation results. The book is a valuable resource to any professional or student involved in high-speed circuit design or anyone trying to learn about CMOS transceivers.
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