Next Generation Assembly Fabrication Methods

Today, the continued success of many industries, especially the microelectronics industry, relies upon the ability to fabricate structures with nanometer precision. The efforts toward developing nanometer scale fabrication methods fall loosely into two fields. One field seeks to extend the current planar, deposit-pattern-etch paradigm used for complementary metal oxide semiconductors (CMOS). This is a top-down approach. The other seeks new techniques to assemble structures without handling individual particles-self-assembly. These techniques take a bottom-up approach. "We are beginning to reach the fundamental limits of the materials used in the planar CMOS process, the process that has been the basis for the semiconductor industry for the past 30 years."2 This is driving industry to fund research to find ways to continue "Moore's Law" - doubling the number of transistors on a chip every two years - with new fabrication methods. The thesis of this paper is that as new fabrication methods are mastered in the quest to continue Moore's Law, these techniques will propagate to other applications with the potential to threaten US national security interests. This paper seeks to prove the thesis with a technology trend forecast in the field of nanoscience focused on self-assembled devices. It identifies a trend, tracks the development of a technology, then forecasts applications, implications, and makes recommendations.