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A partially redundant number system is presented as an internal format for floating point arithmetic operations. The redundant number system is based on signed digits and enables carry free arithmetic operations to improve the performance. A detailed discussion of an adder and a multiplier using the proposed format is provided and the specific challenges of the designs are explained. Beside the redundancy, the proposed units include further enhancements that increase the floating point performance such as a hexadecimal based number format and a postponed rounding technique. Transistor simulation of the complete adder and multiplier confirm the performance advantage predicted by the developed analytical model. The proposed internal format and arithmetic units comply with all the rounding modes of the IEEE floating point standard.
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Angielski
